Design and realization of a 2.4 Gbps - 3.2 Gbps clock and data recovery circuit

This thesis presents the design, verification, system integration and the physical realization of a high-speed monolithic phase-locked loop (PLL) based clock and data recovery (CDR) circuit. The architecture of the CDR has been realized as a two-loop structure consisting of coarse and fine loops, each of which is capable of processing the incoming low-speed reference clock and high-speed random data. At start up, the coarse loop provides fast locking to the system frequency with the help of the reference clock. After the VCO clock reaches a proximity of system frequency , the LOCK signal is generated and the coarse loop is tumed off, while the fine loop is tumed on. Fine loop tracks the phase of the generated clock with respect to the data and aligns the VCO clock such that its rising edge is in the middle of data eye. The speed and symmetry of sub-blocks in fine loop are extremely important, since all asymmetric charging effects, skew and setup/hold problems in this loop translate into a static phase error at the clock output. The entire circuit architecture is built with a special low-voltage circuit design technique. All analogue as well as digital sub-blocks of the CDR architecture presented in this work operate on a differential signalling, which significantly makes the design more complex while ensuring a more robust perforrnance. Other important features of this CDR include small area, single power supply, low power consumption, capability to operate at very high data rates, and the ability to handle between 2.4 Gbps and 3.2 Gbps data rate. The CDR architecture was realized using a conventional 0.13-mikrometer digital CMOS technology (Foundry: UMC), which ensures a lower overall cost and better portability for the design. The CDR architecture presented in this work is capable of operating at sampling frequencies of up to 3.2 GHz, and still can achieve the robust phase alignrnent. The entire circuit is designed with single 1.2 V power supply .The overall power consumption is estimated as 18.6 mW at 3.2 GHz sampling rate. The overall silicon area of the CDR is approximately 0.3 mm^2 with its internal loop filter capacitors. Other researchers have reported similar featured PLL-based clock and data recovery circuits in terms of operating data rate, architecture and jitter performance. To the best of our knowledge, this clock recovery uses the advantage of being the first high-speed CDR designed in CMOS 0.13 mikrometer technology with the superiority on power consumption and area considerations among others. The CDR architecture presented in this thesis is intended, as a state-of-the-art clock recovery for high-speed applications such as optical communications or high bandwidth serial wireline communication needs. It can be used either as a stand-alone single-chip unit, or as an embedded intellectual property (IP) block that can be integrated with other modules on chip

Clinical and molecular evaluation of MEFV gene variants in the Turkish population: a study by the National Genetics Consortium

Familial Mediterranean fever (FMF) is a monogenic autoinflammatory disorder with recurrent fever, abdominal pain, serositis, articular manifestations, erysipelas-like erythema, and renal complications as its main features. Caused by the mutations in the MEditerranean FeVer (MEFV) gene, it mainly affects people of Mediterranean descent with a higher incidence in the Turkish, Jewish, Arabic, and Armenian populations. As our understanding of FMF improves, it becomes clearer that we are facing with a more complex picture of FMF with respect to its pathogenesis, penetrance, variant type (gain-of-function vs. loss-of-function), and inheritance. In this study, MEFV gene analysis results and clinical findings of 27,504 patients from 35 universities and institutions in Turkey and Northern Cyprus are combined in an effort to provide a better insight into the genotype-phenotype correlation and how a specific variant contributes to certain clinical findings in FMF patients. Our results may help better understand this complex disease and how the genotype may sometimes contribute to phenotype. Unlike many studies in the literature, our study investigated a broader symptomatic spectrum and the relationship between the genotype and phenotype data. In this sense, we aimed to guide all clinicians and academicians who work in this field to better establish a comprehensive data set for the patients. One of the biggest messages of our study is that lack of uniformity in some clinical and demographic data of participants may become an obstacle in approaching FMF patients and understanding this complex disease